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Agile Computing Authors: Liz McMillan, Tim Hinds, Flint Brenton, Pat Romanski, David Dodd

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SEMATECH Demonstrates Breakthrough Solutions for Critical Materials in Next Generation Devices at IEDM 2012

Engineers from SEMATECH will present five technical papers at the 58th annual IEEE International Electron Devices Meeting (IEDM), December 10-12, 2012, at the Hilton San Francisco, Union Square.

Significant breakthroughs that address the growing need for high performance, low power devices will be highlighted, including resistive RAM (RRAM) memory technologies, Schottky barrier height modulated contact resistance tuning, advanced quantum well III-V channel FETs for scaled CMOS devices, and future ultra-low power tunneling FET devices.

SEMATECH Presentation:

Title: Methodology for the Statistical Evaluation of the Effect of Random Telegraph Noise (RTN) on RRAM Characteristics
When: Tuesday, December 11, 11:10 a.m.
Where: Continental Ballroom 1-3

This paper introduces a figure of merit to quantify a RRAM instability, a complex multi-level random telegraph noise signal generally observed in read current. A newly developed statistical model allows the maximum size and minimum operating current for a high density RRAM array to be estimated.

Title: Effective Schottky Barrier Height Modulation using Dielectric Dipoles for Source/Drain Specific Contact Resistivity Improvement
When: Tuesday, December 11, 4:25 p.m.
Where: Continental Ballroom 6

This paper analyzes sub-10-8Ω-cm2 and sub-2x10-8Ω-cm2contact resistivity of N-type and P-type Si on 300 mm wafers using an ultra-thin high-k dielectric grown by atomic layer deposition between the metal and Si. The suppression of evanescent metal-induced gap states and formation of an interface dipole are shown to play a significant role in reducing contact resistivity as long as the tunneling resistance of the dielectric stack is kept low.

Title: Microscopic Understanding and Modeling of HfO2 RRAM Device Physics (Invited)
When: Tuesday, December 11, 2:20 p.m.
Where: Imperial Ballroom

A consistent physical description of the chemical/atomistic properties of materials is proposed that explains the microscopic features of forming and set and reset operations, including charge transport across hafnia, oxygen ion migration, and the shape and profile of the conductive filament.

Title: Real-Time Study of Switching Kinetics in Integrated 1T/ HfOx 1R RRAM: Intrinsic Tunability of Set/Reset Voltage and Trade-off with Switching Time
When: Tuesday, December 11, 3:35 p.m.
Where: Imperial Ballroom

A novel real-time methodology is demonstrated to determine intrinsic forming and switching characteristics of HfOx-based RRAMs. Eliminating parasitics in 50 nm x 50 nm cross-bar 1T1R devices on 300 mm wafers using fab-friendly TiN electrodes enables superior control of high and low resistance in the conductive filament. Sub-50fF parasitics also enable a pulsed forming method compatible with high volume manufacturing. RRAM operation trade-offs are assessed.

Title: Benchmarking and Improving III-V Esaki Diode Performance with a Record 2.2 MA/cm2 Peak Current to Enhance TFET Drive Current
When: Wednesday, December 12, 11:35 a.m.
Where: Continental Ballroom 6

This paper reports a comprehensive experimental benchmarking of an Esaki diode, including GaAs, In0.53Ga0.47As, InAs, InAs0.9Sb0.1/Al0.4Ga0.6Sb, and InAs/GaSb. Engineering the hetero-junctions enhances peak and Zener current densities beyond homo-junctions, to a record 2.2 MA/cm2 and 1.1 MA/cm2 (-0.3 V), laying the groundwork for III-V TFETs at the 7 nm technology node.

Title: ETB-QW InAs MOSFET with Scaled Body for Improved Electrostatics
When: Wednesday, December 12, 2:25 p.m.
Where: Continental Ballroom 6

Extremely thin body InAs quantum well (QW) MOSFETs have been demonstrated with improved electrostatics mobility and injection velocity vij down to a 50 nm gate length. This was achieved using 1/3/1 nm InGaAs/InAs/InGaAs QW structures, an optimized layer design, and a high mobility InAs channel.

The IEDM conference draws an international audience of industry professionals for an intensive exploration of design, manufacturing, physics, and modeling of semiconductors and other electronic devices, spotlighting the work of the world’s leading electronics scientists and engineers. It is one of many industry forums SEMATECH uses to collaborate with scientists and engineers from corporations, universities, and other research institutions, many of whom are research partners.


SEMATECH®, the international consortium of leading semiconductor device, equipment, and materials manufacturers, this year celebrates 25 years of excellence in accelerating the commercialization of technology innovations into manufacturing solutions. Through our unwavering commitment to foster collaboration across the nanoelectronics industry, we help our members and partners address critical industry transitions, drive technical consensus, pull research into the industry mainstream, improve manufacturing productivity, and reduce risk and time to market. Information about SEMATECH can be found at or follow us on Twitter @sematechnews.

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